NVIDIA is seeking a Principal System Power Management and Performance Architect to join the Silicon Co-Design Group (SCG). The successful candidate will operate at the intersection of workload behavior, silicon capabilities, firmware policies, and platform constraints to develop architectures that span multiple silicon generations.
The role involves defining the multi-generation roadmap for system-level power and performance features, owning the architecture and integration strategy for HSIO power management, DVFS, P-states, and low-power features, and leading system-level boot and IST architecture.
The ideal candidate will have:
- 15+ years of system architecture, development, and validation experience with a focus on power and performance-per-watt optimization in datacenter or high-performance platforms
- A verifiable history of guiding architecture decisions that shipped across multiple silicon programs
- Extensive knowledge of HSIO power management, DVFS, P-states, system boot flows, and low-power entry/exit architecture
- Strong fundamentals in low-power design, power management techniques, and rack-level performance architecture
NVIDIA offers highly competitive salaries and a comprehensive benefits package, including equity and benefits.
